1. Field of the Invention
The present invention relates to a Group III nitride semiconductor light-emitting device including an embossed substrate.
2. Background Art
In general, a semiconductor light-emitting device includes a substrate; an n-type semiconductor layer, a light-emitting layer, and a p-type semiconductor layer, which layers are deposited in this order on the substrate; and electrodes. Light emitted from the light-emitting layer exits the outside of the device through, for example, outer exposed surfaces (e.g., the upper and side surfaces of the semiconductor layers) or exposed surfaces (e.g., the back surface and side surfaces of the substrate).
When light emitted from the light-emitting layer enters the interface between the semiconductor layer and the electrode or between the semiconductor layer and the substrate at an angle equal to or larger than a specific critical angle, the light propagates, with repeated total reflection, through the interior of the semiconductor layer in a lateral direction; i.e., in a direction parallel to the main surface of the substrate. A portion of the light is absorbed in the semiconductor layer. Thus, the semiconductor light-emitting device exhibits reduced light extraction efficiency.
In view of the foregoing, techniques for improving light extraction efficiency have been developed. For example, Patent Document 1 discloses a semiconductor light-emitting device including a substrate having an embossment on the main surface thereof. Patent Document 1 describes that light propagating in a direction parallel to the main surface of the substrate is reflected by the embossment of the substrate, and the reflected light is emitted in another direction (e.g., in an axial direction) (see paragraph [0021] of Patent Document 1). Also, Patent Document 2 describes a similar technique (see paragraph [0011] of Patent Document 2).    Patent Document 1: Japanese Patent Application Laid-Open (kokai) No. 2002-280611    Patent Document 2: Japanese Patent Application Laid-Open (kokai) No. 2012-160502
As described hereinbelow, the distance between the n-type semiconductor layer and the p-type semiconductor layer at a position where a threading dislocation is present is smaller than that at a position where no threading dislocation is present. Under application of a specific voltage, a stronger electric field is locally generated at a position where the distance between the n-type semiconductor layer and the p-type semiconductor layer is smaller. Thus, electric current is likely to flow at a position where a threading dislocation is present.
When threading dislocation density is lowered in a semiconductor crystal, the semiconductor crystal exhibits improved crystallinity (see paragraph [0005] of Patent Document 2), whereby emission efficiency is improved. Meanwhile, when threading dislocation density is lowered; i.e., the number of threading dislocations, through which electric current is likely to flow, is reduced, driving voltage Vf may be increased (see paragraph [0005] of Patent Document 2). Thus, a trade-off relationship is established between reduction in threading dislocation density and suppression of an increase in driving voltage Vf.